1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device and its operating method, and more particularly to an improvement in the operation of extracting charges from the charge storage portion and to a device that performs this improved operation.
2. Description of the Related Art
FIG. 1 is a sectional view of an ordinary flash EEPROM.
As shown in FIG. 1, an n-type source diffused layer 2 and an n-type drain diffused layer 3 are formed in a p-type silicon substrate 1. On the channel region 4 is formed a first gate insulating film 5. The first gate insulating film 5 has a thickness of, for example, approximately 100 .ANG.. Formed on the first gate insulating film 5 is a floating gate 6, on which a second gate insulating film 7 is formed. On the second gate insulating film 7 is formed a control gate 8.
The operation of the conventional cell of FIG. 1 will be explained.
How to write the data
To write the data, hot electrons are generated near the drain diffused layer 3 by applying a program voltage of, for example, 10 V, to the control gate 8, and a power supply voltage of, for example, 5 V, to the drain diffused layer 3. These hot electrons are injected from the vicinity of the drain diffused layer 3 into the floating gate 6.
How to erase the data
The flow of erasing the data is shown in FIG. 2, and the threshold value for each process is shown in FIG. 3.
First, at step 1, the data is written into all cells. This is done to prevent overerasure of the data by injecting electrons into the floating gates 6 of all 10 cells and then extracting electrons. This action is called preprogramming.
Next, at step 2, with the drain diffused layer 5 open, the control gate 8 is applied with, for example, -10 V, and the source diffused layer 2 is applied with, for example, 5 V, to extract electrons from the floating gate 6 into the source diffused layer 2 by F-N tunnel current.
The erasure at step 2 and the verification at step 3 are repeated at intervals of 10 ms. This is done to prevent overerasure of the data by extracting electrons gradually while verifying whether the data has been overerased. This action is called intelligent erasure. Normally, repetition of erasure and verification is completed in less than one second in total.
How to read the data
The reading of the data is done as follows: with the control gate 8 applied with, for example, 5 V, and the drain diffused layer 3 applied with a reading voltage of, for example, 1 V, a 1 or a 0 is read out, depending on whether current flows through the channel 4.
Overerasure of the data in the flash EEPROM will lead to erroneous reading. For example, after the data has been overerased from an unselected cell, the cell is placed in the ON state, allowing current to flow through the bit line. This makes it impossible to correctly read the information from the selected cell. To avoid this problem, the flash EEPROM employs intelligent erasing techniques.
Although intelligent erasing techniques prevent overerasure of the data, it cannot eliminate variation in the cell threshold value after erasure. As a result, there is variation in the cell threshold value after erasure as shown in FIG. 3.
Such variation stems from the following two factors:
The first factor is variation in the electron-extracting characteristics caused by variation in the film quality of the gate insulating film. The most effective way to suppress this variation is to eliminate variation in the film quality of the gate insulating film by improving the manufacturing processes. At present, there is no process of eliminating variation in the gate insulating film quality. PA1 The second factor is variation in the electron-extracting characteristics caused by variation in the cell work shape. This type of variation may be eliminated by obviating variation in the work shape through improved processing. Like the first factor, such effective processing for the second factor has yet to be developed.
Presently, variation in the cell threshold value after erasure is approximately 2 V at maximum. As more and more cells will be squeezed into a limited space in the future, the deviation of the work shape from the design dimensions would increase. Consequently, variation in the threshold value after erasure would be larger.
As noted above, conventional flash EEPROMs have the problem that variation in the cell threshold value after extraction of electrons becomes larger as a result of variation caused by variation in the gate insulating film quality combining with variation caused by variation in the cell work shape.